Testing signal delays is one way for measuring a circuit's performance. Structures currently exist for testing signal delays in memory circuit such as SRAM cells for use in testing memory circuit performance.
In one example implementation, a circular edge detector is provided for an SRAM having memory columns that are multiplexed (muxed) into a delay path. The signal passes through each column and sets a latch at the output. The clock stops the propagation and generates a thermometer output of the columns traversed.
Such a structure could further be setup as a ring oscillator and the frequency of oscillation can be taken as a secondary measurement.
Such a structure can test delays through the SRAM cells without any actuation or write specific timing. However, it takes much of chip array area.
Further prior art include a circuit and method for path monitoring having selectable modes of operation. In the scheme there is sampled the timing of read operations with no correcting action.
In current implementations of SRAM memory devices implementing an inverter having, for example, a cross-coupled configuration of P-type and N-type field effect transistors, e.g., FinFETs, it is found that increasingly the P and N FinFETs have equivalent drive strengths.
This complicates a write phase because there is no native pull direction for the write operation: the p-type device and n-type device pull on the cell value equally.
As technology nodes become increasingly smaller, and operating voltages decrease, it would be highly desirable to correct such write phase issues and improve write characteristics.